1. Field of the Invention
The present invention relates to a switching power supply circuit, a semiconductor device used for the same, and an LED lighting device using the same.
2. Description of Related Art
Conventionally, in the field of switching power supply circuits, there is disclosed a technique for stabilizing output current with respect to load change, including the steps of detecting time period during which secondary current of a transformer is flowing, and setting a ratio of the time period to a switching period, namely an on-duty ratio of a switching element (see JP-A-2009-11073, which is referred to as Patent document 1 hereinafter).
FIG. 11 is a block diagram illustrating a conventional example of a switching power supply device (FIG. 1 of Patent document 1). A switching power supply device X of this conventional example includes a semiconductor device X100, a transformer X110, diodes X121 and X141, capacitors X122 and X142, and resistors X151 and X152, which constitute a flyback-type switching power supply circuit generating a predetermined DC output voltage Vout from an AC input voltage Vin so as to supply the DC output voltage Vout to a load X130. The transformer X110 includes a primary winding X111, a secondary winding X112, and an auxiliary winding X113.
In the semiconductor device X100, there are integrated a switching element X1, a drain current detection circuit X2, a drain current limiter circuit X3, an error amplifier X4, a pulse frequency modulation (PFM) control circuit X5, a secondary current on-period detection circuit X6, a secondary current detection delay time correction circuit X7, a secondary current on-duty control circuit X8, a clock signal selection circuit X9, a flip-flop circuit X10, a NAND circuit X11, a gate driver X12, a on-time blanking pulse generation circuit X13, an AND circuit X14, and a regulator X15.
FIG. 12 is a circuit diagram illustrating a principal part of the semiconductor device X100 (FIG. 2 of Patent document 1). The secondary current on-period detection circuit X6 includes one-pulse signal generation circuits X21 and X23, a comparator X22, and a flip-flop circuit X24. The secondary current detection delay time correction circuit X7 includes a constant current source X31, a capacitor X32, an inverter X33, and a switch X34. The secondary current on-duty control circuit X8 includes switches X41 and X42, a capacitor X43, a constant current source X44, N-channel metal oxide semiconductor (MOS) field effect transistors X45 and X46, a comparator X47, a reference voltage source X48, an AND circuit X49, and a one-pulse signal generation circuit X50.
FIG. 13 is a timing chart illustrating voltage waveforms and current waveforms of individual portions of the switching power supply device X, which includes in order from the upper, an auxiliary winding voltage VTR obtained by dividing a voltage at an end of the auxiliary winding X113, primary current Ids flowing in the switching element X1, and secondary current I2p flowing in the secondary winding X112. Concerning symbols in FIG. 13, T1 denotes a first period during which the secondary current I2p is flowing, T2 denotes a second period during which the secondary current I2p does not flow, T3 denotes a third period as a sum of the first period T1 and the second period T2, Ipk1 denotes a peak value of the primary current Ids, and Ipk2 denotes a peak value of the secondary current I2p. 
Average output current Tout supplied from the switching power supply device X to the load X130 is an average value of the secondary current I2p. The average value of the secondary current I2p in the first period T1 is ½ of the peak current Ipk2 of the secondary current I2p. The average value of the secondary current I2p in the third period T3 is a value obtained by multiplying the average value of the secondary current I2p in the first period T1 by an on-duty ratio of the switching element X1. Therefore, when the number of turns of the primary winding X111 is denoted by N1, and the number of turns of the secondary winding X112 is denoted by N2, the average output current Iout is expressed by the following expression (1).Iout=(½)×(N1/N2)×(T1/T3)×Ipk1  (1)
The conventional switching power supply device X controls the peak current Ipk1 of the switching element X1 to be constant using the drain current limiter circuit X3 so that T1/T3 in the expression (1) becomes constant, and hence controls the average output current Tout to be constant.
The comparator X22 included in the secondary current on-period detection circuit X6 sets an comparison output signal to a high level (logical level when the secondary current is detected to be off) when the auxiliary winding voltage VTR applied to an inverting input terminal (−) becomes a reference voltage or lower applied to the non-inverting input terminal (+). A waveform of the auxiliary winding voltage VTR gradually drops as time passes after the switching element X1 is turned off as illustrated in FIG. 13. Therefore, there is a delay time ΔT1 from time when the secondary current I2p becomes an actual off state (zero value) until the auxiliary winding voltage VTR becomes lower than the reference voltage of the comparator X22. As a result, in the secondary current on-period detection circuit X6, there occurs the delay time ΔT1 until detection of the off state of the secondary current I2p. 
Therefore, in the conventional switching power supply device X, a delay correction period ΔT2 corresponding to the delay time ΔT1 is subtracted from an on-period of the secondary current I2p detected by the comparator X22 in advance. Thus, the on-period of the secondary current I2p is corrected so that accuracy of the average output current Tout is enhanced.
Here, as illustrated in FIG. 13, when an on-period of the switching element X1 is denoted by T4, in one period of switching drive, an average input current Iin flowing into the switching power supply device X is expressed by the following expression (2).
                                                        Iin              =                            ⁢                                                (                                      1                    /                    2                                    )                                ×                Ipk                ⁢                                                                  ⁢                1                ×                                  (                                      T                    ⁢                                                                                  ⁢                                          4                      /                      T                                        ⁢                                                                                  ⁢                    3                                    )                                                                                                        =                            ⁢                                                (                                      1                    /                    2                                    )                                ×                Ip                ⁢                                                                  ⁢                1                ×                                  (                                      T                    ⁢                                                                                  ⁢                                          1                      /                      T                                        ⁢                                                                                  ⁢                    3                                    )                                ×                                  (                                      N                    ⁢                                                                                  ⁢                                          1                      /                      N                                        ⁢                                                                                  ⁢                    2                                    )                                ×                                  (                                      Vout                    /                    Vin                                    )                                                                                        (        2        )            
Here, it is supposed that the input voltage Vin of the switching power supply device X is changed. As described above, the conventional switching power supply device X controls the peak current Ipk1 of the switching element X1 to be constant using the drain current limiter circuit X3 so that T1/T3 in the above expression (1) is constant, and hence controls the average output current Tout to be constant. In addition, N1/N2 is also constant. Further, because the average output current Iout flowing in the load X130 is constant, the output voltage Vout is also constant. Therefore, it is understood that if the input voltage Vin of the switching power supply device X is changed, the average input current Iin of the switching power supply device X changes inversely proportional to the input voltage Vin.
However, in a power supply circuit supplied with AC power, a power factor thereof is important. In order to obtain a high power factor, it is desirable that the power supply circuit should look like a pure resistance viewed from the AC power supply side. In other words, it is necessary that input current of the power supply circuit is proportional to the input voltage.
In view of the above discussion, the conventional switching power supply device X has a problem that the power factor is bad when the AC power is input, and hence power loss in a power supply system from a power station to a terminal product (load) is increased, and further noise jamming occurs in other devices.